Intel, the world's biggest semiconductor maker, said on Monday that it had succeeded in building a test chip that packs 10 million transistors into an area the size of the tip of a ball-point pen.
Intel, based in Santa Clara, California, has made the first working memory chip that uses so-called 65-nanometer technology to shrink the circuits inside chips, said Mark Bohr, an Intel researcher. The method lets Intel pack twice as many transistors into the same space as previous technology, reports International Herald Tribune.
According to the Xinhua News, "The achievement extends Intel's effort to drive the development of new manufacturing process technology every two years, in accordance with Moore's Law," Intel said in a statement.
The transistors in the new 65nm technology have gates, the switch that turns a transistor on and off, measuring 35nm, approximately 30 percent smaller than the gate lengths on the previous 90nm technology, according to Intel.
A nanometer is one-billionth of a meter. Sixty-five nanometer (nm) process technology is now the most advanced in the world. Intel said the new process technology increases the number of tiny transistors squeezed onto a single chip, giving the company the foundation on which to deliver future multi-core processors and to design new features into future products, including virtualization and security capabilities.
Intel said its new 65nm process technology also includes several unique power-saving and performance-enhancing features.
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